1. Field
The present invention relates to a memory array using a mechanical switch and a method for operating thereof, and more particularly, to a method for performing a reading, a writing, an erasing operation of the memory array, and a selecting operation of a multi-bit and a single memory cell.
2. Description of the Background Art
Until now, a degree of integration of a semiconductor transistor greatly increases according to Moore's law, thereby much contributing to the development of a semiconductor industry. In general, the semiconductor transistor has been used as a switching device using an on or off characteristic and an amplifying device using a current and voltage amplification characteristic. In a digital integration circuit particularly, the semiconductor transistor has been mainly used as the switching device. However, the semiconductor transistor has a drawback that it should be necessarily formed on a semiconductor substrate and thus, should consider a body effect of the semiconductor substrate. Particularly, the semiconductor transistor has a drawback of a leakage of electrical charges inevitably caused by its internal leakage source. In addition, the semiconductor transistor has a drawback that its sensitivity to an external harmful environment such as radiation causes a soft error rate (SER). The semiconductor transistor has a drawback that a degradation of its gate oxide film causes a reduction of an electrical reliability, and an increase of the degree of integration causes a short channel effect such as a reduction of a sub-threshold swing and hot election injection.
In order to overcome conventional several drawbacks of the semiconductor transistor serving as the switching device, a mechanical switch using a recent Micro-Electro-Mechanical System (MEMS) or Nano-Electro-Mechanical System (NEMS) is being researched and developed.
FIG. 1 is a conceptual diagram illustrating a conventional mechanical switch Referring to FIG. 1, the conventional mechanical switch, which is disclosed in U.S. Pat. No. 6,534,839 and W. H. Teh, et. al., “Switching characteristics of electrostatically actuated miniaturized micromechanical metallic catilevers”, J. Vac. Sci. Technol., B. 21, pp. 2360-2367, 2003, is of a structure comprising a gate electrode 10, a drain electrode 30, and a source electrode 20 comprised of an anchor part 21 and a mobile part 22. An operation of the mechanical switch is characterized in that the mobile part 22 of the source electrode 20 electrically contacts with the drain electrode 30, thereby electrically conducting the source electrode 20 and the drain electrode 30 in generation of an electrostatic force based on a pull-in voltage Vpi difference between the gate electrode 10 and the source electrode 20, and the source electrode 20 and the drain electrode 30 are electrically disconnected in the absence of the generation of the electrostatic force. Herein, the pull-in voltage can be defined as the voltage difference between the source electrode 20 and the gate electrode 10, required for electrically conducting the source electrode 20 and the drain electrode 30 of the mechanical switch.
The pull-in state occurs when the mobile part 22 of the source electrode 20 shifts by one third of a distance between the mobile part 22 of the source electrode 20 and the gate electrode 10. The pull-in voltage is similar in function with a threshold voltage of a metal oxide semiconductor (MOS) transistor (H. C. Nathanson, et al, “The resonant gate transistor”, IEEE Transactions on Electron Devices, Vol. ED-104, No. 3, pp. 117-133, 1967).
Recently, U.S. Pat. No. 6,509,605 discloses a memory array constructed using a mechanical switch, in which an operation voltage is low and an operation speed is fast and thus, a power consumption is low and writing and reading time are short as well as an electrical reliability is not deteriorated because of mechanical actuation, and a sensitivity to radiation is poor. The memory array is being researched and developed as a next generation memory array to replace a conventional memory array.
However, the memory array of U.S. Pat. No. 6,509,605 cannot be controlled because of its construction using only the mechanical switch and thus, has a drawback in that it should be constructed in combination with a complementary metal oxide semiconductor (CMOS) transistor. Accordingly, the memory array of U.S. Pat. No. 6,509,605 gets so complex in construction and process and causes a scaling limit, thereby reducing a degree of integration.
In order to overcome the drawback, Korea Patent No. 10-0651825 (i.e., memory array using a mechanical switch and method for controlling thereof, display device using a mechanical switch and method for controlling thereof) as described in FIG. 3 is proposed.
FIG. 2 is a circuit diagram illustrating a conventional memory array using a MOS transistor. Referring to FIG. 2, an input voltage of a source voltage or a ground voltage is applied to a bit line B/L0 connected to a selected MOS transistor of a memory cell 90, and a threshold voltage or more of the MOS transistor is applied to a word line W/L0 connected to the selected MOS transistor. Thus, the applied voltage of the bit line B/L0 is transferred to a storage unit 80 through electrically conducted source electrode 60 and drain electrode 70, and the applied voltage of the bit line B/L0 is stored in the storage unit 80. Less than the threshold voltage is applied to word lines (W/L1 and W/L2) not connected to the selected MOS transistor. Thus, the source electrode 60 and the drain electrode 70 electrically disconnect with each other, and the applied voltage of the bit line is not transferred to the storage unit 80.
The configuration of the memory array using a mechanical switch described in FIG. 3 is different from that of the memory array using a MOS transistor described in FIG. 2 and thus, a control method using a mechanical switch described in FIG. 3 is different from that of the memory array using a MOS transistor described in FIG. 2. Therefore, a method for effectively controlling the memory array using the mechanical switch described in FIG. 3 is being required.